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tlv1171 www.ti.com sbvs177 ? april 2012 1-a, positive fixed-voltage, low-dropout regulator 1 features description the tlv1171 low-dropout (ldo) linear regulator is a 2 ? accuracy: 1.5% (typ) low input voltage version of the popular 1117 voltage ? low i q : 100 a (max) regulator. ? 500x lower than standard 1117 devices the tlv1171 is an extremely low-power device that ? v in : 2.0 v to 5.5 v consumes 500x lower quiescent current than the ? absolute maximum v in : 6.0 v traditional 1117 voltage regulator, making the tlv1171 suitable for applications that mandate very ? stable with 0-ma output current low standby current. the tlv1171 ldo is also stable ? low dropout: 455 mv at 1 a for v out = 3.3 v with 0 ma of load current; there is no minimum load ? high psrr: 65 db at 1 khz requirement, making the device an ideal choice for applications where the regulator is required to power ? minimum ensured current limit: 1.1 a very small loads during standby in addition to large ? stable with cost-effective ceramic capacitors: currents on the order of 1 a during normal operation. ? with 0- esr the tlv1171 offers excellent line and load transient performance, resulting in very small magnitude output ? temperature range: ? 40 c to +125 c voltage undershoots and overshoots when the load ? thermal shutdown and overcurrent protection current requirement changes from less than 1 ma to ? available package: sot223 more than 500 ma. ? see the package option addendum at the a precision band gap and error amplifier provides end of this document for a complete list of 1.5% accuracy. a very high power-supply rejection available voltage options. ratio enables the device to be used for post- regulation after a switching regulator. other valuable applications features include low output noise and low-dropout voltage. ? set top boxes the device is internally compensated to be stable ? tvs and monitors with 0- equivalent series resistance (esr) ? pc peripherals, notebooks, and motherboards capacitors. these key advantages enable the use of ? modems and other communication products cost-effective, small-size ceramic capacitors. cost- effective capacitors that have higher bias voltages ? switching power-supply post-regulation and temperature derating can also be used if desired. the tlv1171 is available in a sot223 package. for alternate pin outs of the device, refer to the tlv1117lv . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. tlv1171xxdcy vout vin 2 3 1 gnd gnd
tlv1171 sbvs177 ? april 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) product v out tlv1171 vvyyyz vv is the nominal output voltage (for example, 33 = 3.3 v). yyy is the package designator. z is the package quantity. use r for reel (2500 pieces), and t for tape (250 pieces). (1) for the most current package and ordering information see the package option addendum at the end of this document, or visit the device product folder at www.ti.com . absolute maximum ratings (1) at t j = +25 c, unless otherwise noted. all voltages are with respect to gnd. value min max unit input voltage range, v in ? 0.3 +6.0 v voltage output voltage range, v out ? 0.3 +6.0 v current maximum output current, i out internally limited output short-circuit duration indefinite continuous total power dissipation p diss see thermal information table operating junction, t j ? 55 +150 c temperature storage, t stg ? 55 +150 c human body model (hbm) 2 kv qss 009-105 (jesd22-a114a) electrostatic discharge (esd) ratings charged device model (cdm) 500 v qss 009-147 (jesd22-c101b.01) (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. thermal information tlv1171 thermal metric (1) dcy (sot223) units 3 pins ja junction-to-ambient thermal resistance 62.9 jctop junction-to-case (top) thermal resistance 47.2 jb junction-to-board thermal resistance 12.0 c/w jt junction-to-top characterization parameter 6.1 jb junction-to-board characterization parameter 11.9 jcbot junction-to-case (bottom) thermal resistance n/a space (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953a . 2 submit documentation feedback copyright ? 2012, texas instruments incorporated
tlv1171 www.ti.com sbvs177 ? april 2012 electrical characteristics at t a = +25 c, v in = v out(typ) + 1.5 v, i out = 10 ma, and c out = 1.0 f, unless otherwise noted. tlv1171 parameter test conditions min typ max unit v in input voltage range 2.0 5.5 v v out > 2 v ? 1.5 +1.5 % v out dc output accuracy 1.5 v v out < 2 v ? 2 +2 % 1.2 v v out < 1.5 v ? 40 +40 mv v o / v in line regulation v out(nom) + 0.5 v v in 5.5 v, i out = 10 ma 1 5 mv v o / i out load regulation 0 ma i out 1 a 1 35 mv i out = 200 ma 115 mv i out = 500 ma 285 mv v out < 3.3 v i out = 800 ma 455 mv i out = 1 a 570 800 mv v do dropout voltage (1) v in = 0.98 x v out(nom) i out = 200 ma 90 mv i out = 500 ma 230 mv v out 3.3 v i out = 800 ma 365 mv i out = 1 a 455 700 mv i cl output current limit v out = 0.9 v out(nom) 1.1 a i q quiescent current i out = 0 ma 50 100 a psrr power-supply rejection ratio v in = 3.3 v, v out = 1.8 v, i out = 500 ma, f = 100 hz 65 db v n output noise voltage bw = 10 hz to 100 khz, v in = 2.8 v, v out = 1.8 v, i out = 500 ma 60 v rms t str startup time (2) c out = 1.0 f, i out = 1 a 100 s uvlo undervoltage lockout v in rising 1.95 v shutdown, temperature increasing +165 c thermal shutdown t sd temperature reset, temperature decreasing +145 c operating junction t j ? 40 +125 c temperature (1) v do is measured for devices with v out(nom) = 2.5 v so that v in = 2.45 v. (2) startup time is the time from when v in asserts to when output is sustained at a value greater than or equal to 0.98 v out(nom) . copyright ? 2012, texas instruments incorporated submit documentation feedback 3
tlv1171 sbvs177 ? april 2012 www.ti.com pin configuration dcy package sot223 (top view) pin descriptions name pin description gnd 2, tab ground pin input pin. in 1 see the input and output capacitor requirements section for more details. regulated output voltage pin. out 3 see the input and output capacitor requirements section for more details. functional block diagram figure 1. block diagram 4 submit documentation feedback copyright ? 2012, texas instruments incorporated vout vin 2 3 1 gnd gnd current limit bandgap thermal shutdown in out logic gnd tlv1171 series uvlo
tlv1171 www.ti.com sbvs177 ? april 2012 typical characteristics at t a = +25 c, v in = v out(typ) + 1.5 v; i out = 10 ma, and c out = 1.0 f, unless otherwise noted. line regulation line regulation figure 2. figure 3. load regulation dropout voltage vs input voltage figure 4. figure 5. dropout voltage vs output current output voltage vs temperature figure 6. figure 7. copyright ? 2012, texas instruments incorporated submit documentation feedback 5 0 100 200 300 400 500 600 700 1000 output current (ma) 1.9 1.85 1.8 1.75 1.7 output voltage (v) +125 c +85 c +25 c 40 c - 800 900 v = 1.8 v out 2 2.5 3 3.5 4 4.5 12001000 800600 400 200 0 dropout voltage (mv) input voltage (v) +85 c +25 c 40 c - 600500 400 300 200 100 0 dropout voltage (mv) 0 100 200 300 400 500 600 700 800 900 1000 output current (ma) +125 c +85 c +25 c 40 c - - 40 - 25 - 10 5 20 35 65 95 125 temperature ( )c 1.9 1.85 1.8 1.75 1.7 output voltage (v) v = 1.8 v out 50 80 110 10 ma 500 ma 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) 1.9 1.85 1.8 1.75 1.7 output voltage (v) +125 c +85 c +25 c 40 c - v = 1.8 v i = 10 ma out out 3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5 input voltage (v) 1.9 1.85 1.8 1.75 1.7 output voltage (v) +85 c +25 c 40 c - v = 1.8 v i = 1 a out out 4.5 4.9 5.3
tlv1171 sbvs177 ? april 2012 www.ti.com typical characteristics (continued) at t a = +25 c, v in = v out(typ) + 1.5 v; i out = 10 ma, and c out = 1.0 f, unless otherwise noted. quiescent current vs output current current limit vs input voltage figure 8. figure 9. psrr vs frequency psrr vs frequency figure 10. figure 11. psrr vs output current spectral noise density vs frequency figure 12. figure 13. 6 submit documentation feedback copyright ? 2012, texas instruments incorporated 600500 400 300 200 100 0 quiescent current ( a) m 0 100 200 300 400 500 600 700 800 900 1000 output current (ma) +125 c +85 c +25 c 40 c - 3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5 input voltage (v) 1.8 1.781.76 1.74 1.72 1.7 1.681.66 1.64 1.62 1.6 current limit (ma) 4.5 4.9 5.3 +85 c +25 c 40 c - 10 100 1 k 100 k 1 m 10 m frequency (hz) 9080 70 60 50 40 30 20 10 0 power-supply rejection ratio (db) 10 k v v = 3 v - in out i = 500 ma i = 150 ma i = 30 ma out out out 10 100 1 k 100 k 1 m 10 m frequency (hz) 9080 70 60 50 40 30 20 10 0 power-supply rejection ratio (db) 10 k v v = 1.5 v - in out i = 500 ma i = 150 ma i = 30 ma out out out 0 100 200 300 400 500 600 700 800 900 1000 output current (ma) 9080 70 60 50 40 30 20 10 0 power-supply rejection ratio (db) v v = 1.5 v - in out f = 120 hz f = 50 hz f = 10 khz f = 10 mhz f = 1 khz f = 100 khz f = 1 mhz 10 1 0.1 0.01 0.001 noise spectral density ( v/ ) m ? hz 10 100 1 k 10 k 100 k 1 m 10 m frequency (hz)
tlv1171 www.ti.com sbvs177 ? april 2012 typical characteristics (continued) at t a = +25 c, v in = v out(typ) + 1.5 v; i out = 10 ma, and c out = 1.0 f, unless otherwise noted. load transient response load transient response (200 ma to 500 ma, c out = 1 f) (200 ma to 500 ma, c out = 10 f) figure 14. figure 15. load transient response load transient response (1 ma to 500 ma, c out = 1 f) (1 ma to 500 ma, c out = 10 f) figure 16. figure 17. load transient response load transient response (200 ma to 1 a, c out = 1 f) (200 ma to 1 a, c out = 10 f) figure 18. figure 19. copyright ? 2012, texas instruments incorporated submit documentation feedback 7 v = 2.8 v in 50 s/div m 50 mv/div 200 ma/div i out v out 200 ma 500 ma v = 2.8 v in 50 s/div m 50 mv/div 200 ma/div i out v out 200 ma 500 ma v = 2.8 v in 50 s/div m 50 mv/div 500 ma/div i out v out 1 ma 500 ma 50 s/div m 50 mv/div 500 ma/div i out v out 1 ma 500 ma 50 s/div m 100 mv/div 500 ma/div i out v out 200 ma 1 a 50 s/div m 100 mv/div 500 ma/div i out v out 200 ma 1 a
tlv1171 sbvs177 ? april 2012 www.ti.com typical characteristics (continued) at t a = +25 c, v in = v out(typ) + 1.5 v; i out = 10 ma, and c out = 1.0 f, unless otherwise noted. load transient response load transient response (1 ma to 1 a, c out = 1 f) (1 ma to 1 a, c out = 10 f) figure 20. figure 21. line transient response line transient response (v out = 1.8 v, i out = 10 ma) (v out = 1.8 v, i out = 500 ma) figure 22. figure 23. line transient response line transient response (v out = 1.8 v, i out = 1 a) (v out = 1.8 v, i out = 10 ma) figure 24. figure 25. 8 submit documentation feedback copyright ? 2012, texas instruments incorporated 50 s/div m 100 mv/div 500 ma/div i out v out 1 ma 1 a 50 s/div m 100 mv/div 500 ma/div i out v out 1 ma 1 a 200 s/div m 5 mv/div 1 v/div v in v out 3.3 v 4.3 v 200 s/div m 5 mv/div 1 v/div v in v out 3.3 v 4.3 v 200 s/div m 10 mv/div 1 v/div v in v out 3.3 v 4.3 v 200 s/div m 10 mv/div 1 v/div v in v out 3.3 v 5.5 v
tlv1171 www.ti.com sbvs177 ? april 2012 typical characteristics (continued) at t a = +25 c, v in = v out(typ) + 1.5 v; i out = 10 ma, and c out = 1.0 f, unless otherwise noted. line transient response line transient response (v out = 1.8 v, i out = 500 ma) (v out = 1.8 v, i out = 1 a) figure 26. figure 27. copyright ? 2012, texas instruments incorporated submit documentation feedback 9 200 s/div m 10 mv/div 1 v/div v in v out 3.3 v 5.5 v 200 s/div m 10 mv/div 1 v/div v in v out 3.3 v 5.5 v
tlv1171 sbvs177 ? april 2012 www.ti.com application information the tlv1171 is a low quiescent current linear regulator designed for high-current applications. unlike typical high-current linear regulators, the tlv1171 consumes significantly less quiescent current. the device delivers excellent line and load transient performance. the tlv1171 is low noise, and exhibits a very good power-supply rejection ratio (psrr). as a result, the device is ideal for high-current applications that require very sensitive power-supply rails. the tlv1171 regulator offers both current limit and thermal protection. the device operating junction temperature range is ? 40 c to +125 c. input and output capacitor requirements for stability, 1.0- f ceramic capacitors are required at the output. higher-valued capacitors improve transient performance. x5r- and x7r-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (esr) over temperature. unlike traditional linear regulators that need a minimum esr for stability, the tlv1171 is ensured to be stable with no esr. therefore, cost- effective ceramic capacitors can be used with this device. effective output capacitance that takes bias, temperature, and aging effects into consideration must be greater than 0.5 f to ensure device stability. although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1- f to 1.0- f, low-esr capacitor across the in and gnd pins of the regulator. this capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. a higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated, or if the device is not located physically close to the power source. if source impedance is greater than 2 , a 0.1- f input capacitor may also be necessary to ensure stability. board layout recommendations to improve psrr and noise performance input and output capacitors should be placed as close to the device pins as possible. to improve characteristic ac performance such as psrr, output noise, and transient response, it is recommended that the board be designed with separate ground planes for v in and v out , with the ground plane connected only at the gnd pin of the device. in addition, the output capacitor ground connection should be connected directly to the device gnd pin. higher-value esr capacitors may degrade psrr performance. internal current limit the tlv1171 internal current limit helps to protect the regulator during fault conditions. during current limit, the output sources a fixed amount of current that is largely independent of the output voltage. in such a case, the output voltage is not regulated and can be calculated by equation 1 : (1) the pmos pass transistor dissipates [(v in ? v out ) i limit ] until thermal shutdown is triggered and the device turns off. as the device cools down, it is turned on by the internal thermal shutdown circuit. if the fault condition continues, the device cycles between current limit and thermal shutdown. see the thermal information section for more details. the pmos pass element in the tlv1171 has a built-in body diode that conducts current when the voltage at out exceeds the voltage at in. this current is not limited; if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. 10 submit documentation feedback copyright ? 2012, texas instruments incorporated v = i r out limit load
tlv1171 www.ti.com sbvs177 ? april 2012 dropout voltage the tlv1171 uses a pmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the pmos pass device is in the linear region of operation and the input-to-output resistance is the r ds(on) of the pmos pass element. v do scales approximately with output current because the pmos device behaves like a resistor in dropout. as with any linear regulator, psrr and transient response are degraded as (v in ? v out ) approaches dropout. transient response as with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude. undervoltage lockout (uvlo) the tlv1171 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry operates properly. thermal information thermal protection disables the output when the junction temperature rises to approximately +165 c, thus allowing the device to cool. when the junction temperature cools to approximately +145 c, the output circuitry is again enabled. depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. this cycling limits dissipation of the regulator, protecting it from damage as a result of overheating. any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. for reliable operation, junction temperature should be limited to +125 c (max). to estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. the tlv1171 internal protection circuitry has been designed to protect against overload conditions. it is not intended to replace proper heatsinking. continuously running the tlv1171 into thermal shutdown degrades device reliability. power dissipation the ability to remove heat from the die is different for each package type and presents different considerations in the printed circuit board (pcb) layout. the pcb area around the device that is free of other components moves heat from the device to ambient air. performance data for jedec low and high-k boards are given in the thermal information table. using heavier copper increases the effectiveness in removing heat from the device. the addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. power dissipation depends on input voltage and load conditions. power dissipation (p d ) is equal to the product of the output current and voltage drop across the output pass element, as shown in equation 2 : (2) copyright ? 2012, texas instruments incorporated submit documentation feedback 11 p = (v v ) i - d in out out
package option addendum www.ti.com 19-nov-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv117112dcyr active sot-223 dcy 4 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 yx TLV117112DCYT active sot-223 dcy 4 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 yx tlv117115dcyr active sot-223 dcy 4 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 c9 tlv117115dcyt active sot-223 dcy 4 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 c9 tlv117118dcyr active sot-223 dcy 4 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 wf tlv117118dcyt active sot-223 dcy 4 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 wf tlv117125dcyr active sot-223 dcy 4 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 we tlv117125dcyt active sot-223 dcy 4 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 we (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 19-nov-2014 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv117112dcyr sot-223 dcy 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 TLV117112DCYT sot-223 dcy 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 tlv117118dcyr sot-223 dcy 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 tlv117118dcyt sot-223 dcy 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 tlv117125dcyr sot-223 dcy 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 tlv117125dcyt sot-223 dcy 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 q3 package materials information www.ti.com 20-nov-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tlv117112dcyr sot-223 dcy 4 2500 340.0 340.0 38.0 TLV117112DCYT sot-223 dcy 4 250 340.0 340.0 38.0 tlv117118dcyr sot-223 dcy 4 2500 340.0 340.0 38.0 tlv117118dcyt sot-223 dcy 4 250 340.0 340.0 38.0 tlv117125dcyr sot-223 dcy 4 2500 340.0 340.0 38.0 tlv117125dcyt sot-223 dcy 4 250 340.0 340.0 38.0 package materials information www.ti.com 20-nov-2014 pack materials-page 2
mechanical data mpds094a ? april 2001 ? revised june 2002 post office box 655303 ? dallas, texas 75265 dcy (r-pdso-g4) plastic small-outline 4202506/b 06/2002 6,30 (0.248) 6,70 (0.264) 2,90 (0.114) 3,10 (0.122) 6,70 (0.264) 7,30 (0.287) 3,70 (0.146) 3,30 (0.130) 0,02 (0.0008) 0,10 (0.0040) 1,50 (0.059) 1,70 (0.067) 0,23 (0.009) 0,35 (0.014) 1 2 3 4 0,66 (0.026) 0,84 (0.033) 1,80 (0.071) max seating plane 0 ?10 gauge plane 0,75 (0.030) min 0,25 (0.010) 0,08 (0.003) 0,10 (0.004) m 2,30 (0.091) 4,60 (0.181) m 0,10 (0.004) notes: a. all linear dimensions are in millimeters (inches). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec to-261 variation aa.

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